441 research outputs found

    On ABC spectral radius of uniform hypergraphs

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    Given a kk-uniform hypergraph GG with vertex set [n][n] and edge set E(G)E(G), the ABC tensor ABC(G)\mathcal{ABC}(G) of GG is the kk-order nn-dimensional tensor with \mathcal{ABC}(G)_{i_1, \dots, i_k}= \begin{cases} \dfrac{1}{(k-1)!}\sqrt[k]{\dfrac{\sum_{i\in e}d_{i}-k}{\prod_{i\in e}d_{i}}} & \mbox{if $e\in E(G)$} 0 & \mbox{otherwise} \end{cases} for ij∈[n]i_j\in [n] with j∈[k]j\in [k], where did_i is the degree of vertex ii in GG. The ABC spectral radius of a uniform hypergraph is the spectral radius of its ABC tensor. We give tight lower and upper bounds for the ABC spectra radius, and determine the maximum ABC spectral radii of uniform hypertrees, uniform non-hyperstar hypertrees and uniform non-power hypertrees of given size, as well as the maximum ABC spectral radii of unicyclic uniform hypergraphs and linear unicyclic uniform hypergraphs of given size, respectively. We also characterize those uniform hypergraphs for which the maxima for the ABC spectral radii are actually attained in all cases

    Accelerated hardware video object segmentation: From foreground detection to connected components labelling

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    This is the preprint version of the Article - Copyright @ 2010 ElsevierThis paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integrates the detection of foreground pixels with the labelling of objects using a connected components algorithm. The background models are based on 24-bit RGB values and 8-bit gray scale intensity values. A multimodal background differencing algorithm is presented, using a single FPGA chip and four blocks of RAM. The real-time connected component labelling algorithm, also designed for FPGA implementation, run-length encodes the output of the background subtraction, and performs connected component analysis on this representation. The run-length encoding, together with other parts of the algorithm, is performed in parallel; sequential operations are minimized as the number of run-lengths are typically less than the number of pixels. The two algorithms are pipelined together for maximum efficiency
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